IEEE VLSI Test Symposium (VTS)

At the end of April I attended the 44th IEEE VLSI Test Symposium (VTS) in Napa, CA (April 27–29), where I presented our paper “Experimental Validation of Spatial Autocorrelation Framework for RowHammer Test Optimization.” In this work we show that it is possible to reduce RowHammer test time by sampling only 16K contiguous rows per bank while still preserving the full‑bank spatial structure of vulnerabilities, and that pattern selection needs to be vendor‑aware to avoid large coverage loss in some devices. I especially appreciated the discussions with colleagues from Micron and Cisco about extending RowHammer characterization to newer memories and about securing in‑field test infrastructures in advanced 2D, 2.5D, and 3D systems, as well as conversations with researchers from IBM and KIT on memory reliability and hardware security. These interactions gave me several new ideas for future projects with my lab at Florida Polytechnic University. Many thanks to the VTS 2026 organizers and volunteers for an excellent event, especially Naghmeh Karimi and Yervant Zorian for their leadership and support, and to everyone who shared feedback and questions during the sessions and breaks.

🚀 We are thrilled to share that the TWINRELECT project was well-represented at the 44th IEEE VLSI Test Symposium (VTS)! This conference provided a fantastic platform to showcase our latest research and engage with the global reliability community. Our presence was highlighted by a dedicated session titled "Reliability Analysis and Hardening of Neural Network for Radiation-Critical Systems". The session was expertly chaired by Luigi Dilillo and featured three insightful presentations from our team: 🔹 Douglas Almeida dos Santos presented "Reliability Evaluation of Vector-Accelerated Neural Network Inference on a Fault-Tolerant RISC-V SoC for Space Applications" 🔹 Nikolaos Chatzivangelis presented "Soft Error Reliability Analysis & Hardening of NVDLA MAC Units"  🔹 Nikolaos Zazatis presented "Cross-Layer Reliability Analysis of Slimmable Neural Networks under Permanent Faults" 🤝 Beyond the technical sessions, the symposium was a golden opportunity for our researchers to meet and exchange ideas with renowned experts in the reliability field. These discussions are vital for pushing the boundaries of resilient electronics and fostering international collaboration. 🙏 A huge thank you to the organizers of the IEEE VTS for hosting such a successful and stimulating event. We look forward to continuing these important conversations! University of Thessaly One Planet Thessaly #TWINRELECT #HorizonEurope #IEEEVTS #VTS2026 #Reliability #NeuralNetworks #SpaceTech #RISCV #Semiconductors

And here we have Michael with the poster "From Components to Architecture: An End-to-End Approach to Soft-Error Tolerance" https://lnkd.in/eahVK6JJ & https://lnkd.in/eUcaJKmm submitted to the McCluskey PhD Competition Semifinals & on the wine train 🍷 at #VTS2026 !

Michael @MikeRogenmoser recently participated at the VLSI Test Symposium 2026 in Napa presenting his work "Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection. You can now find his slides here https://lnkd.in/eQcgqKTm

Back from the 44th IEEE VLSI Test Symposium (VTS), the third international test symposium of this academic year and the one targeting the North American region.  A pleasure to join this edition in charming Napa, set in the spectacular #NapaValley wine region in close proximity to #SiliconValley, the citadel of #ChipDesign and the Stanford University technological ecosystem. 🌉 🇺🇸 This year, we contributed by organizing the #TAICHIP Special Session "#Reliability Assessment of #DNN Models and Inference on #SystolicArrays", and I served as a speaker for the TalTech part. 🎤 „SAFPA: Fast #Analytical Reliability Assessment for DNN Inference on Systolic Arrays“, Natalia Cherezova, Artur Jutman, Maksim Jenihhin (TalTech) 🔹 „Iterative and Conservative Statistical Fault Injections for DNN Reliability Assessments“, Annachiara Ruospo, Lorenzo Fezza, Ernesto Sanchez, Matteo Sonza Reorda (PoliTo) 🔹 „FLAUERS: A Novel Fault Injection Technique for Systolic Array Accelerated DNNs“, Salvatore Pappalardo, Bastien Deveautour, Alberto Bosio (ECLyon) Jaan Raik, thank you for moderating the session smoothly! A further contribution was a joint PoliTo-TalTech paper, another great outcome of Josie Esteban Rodriguez Condia's research visit to Tallinn in 2025 and the new collaboration established by Esteban and Mohammad Hasan Ahmadilivani. Looking forward to the next steps! „FT-Sparse: Algorithm-Based Fault Tolerance for Sparse CNNs Using Structured Sparsity in GPUs“ J. E. Rodriguez Condia, M. H. Ahmadilivani, M. Jenihhin, J. Raik, M. Sonza Reorda 🔗 Technical program: https://lnkd.in/eQtdmxjf Naghmeh Karimi, Jennifer Dworak, Arani Sinha, Marcello Traiola, Yervant Zorian, and the entire team, congratulations on the remarkable organization! The combination of keynotes and panels from semiconductor industry leaders alongside the technical sessions was inspiring, and the wine train adventure was a social activity to remember! #EDA, #EdgeAI, #HardwareTesting, TAICHIP Twinning Project, TIRAMISU MSCA Doctoral Network, TalTech School of IT, #CRASHLESS, #TECHteam  

🌍 TARAN Research Group at VTS 2026 🎉 We’re excited to share TARAN’s strong presence at the IEEE VLSI Test Symposium (VTS) 2026, highlighting both our research contributions and service to the test and reliability community. 🔬 Research spotlight: Our Rafael presented the paper "ENFOR-SA: End-to-end Cross-layer Transient Fault Injector for Efficient and Accurate DNN Reliability Assessment on Systolic Arrays" by Rafael Billig Tonetto, Marcello Traiola, Fernando Fernandes, Angeliki Kritikakou ENFOR-SA enables DNN reliability analysis that is as accurate as RTL-level fault injection while remaining nearly as fast as software-level approaches, combining cross-layer simulation with selective RTL usage to achieve scalable, efficient, and practical fault analysis for modern AI accelerators. The tool is publicly available, supporting open and reproducible research. Check the paper: https://lnkd.in/eV745xj3 And the code: https://lnkd.in/ec9biGge 🤝 Community roles: We are also proud of our team’s contributions to the conference organization, with Angeliki serving as Registration Chair, Marcello as Program Chair, and Rafael chairing technical sessions. A big thank you to the VTS community for the engaging discussions and to everyone who stopped by to learn more about our work. #TARAN #VTS #conference #research #IEEE #Reliability #test

It was a pleasure to attend and present at IEEE VLSI Test Symposium (VTS) 2026 this year in Napa Valley! A conference that always brings together some of the best minds in semiconductor test and reliability. I had the opportunity to present two papers, in two different roles. 🎓 As a co-author, I presented "New Techniques for Software Test Library Compaction" in the Late Breaking Results session. This work was carried out together with my colleagues Nick Deligiannis, Mansour Sohrabian, Riccardo Cantoro, and Matteo Sonza Reorda from the CAD & Reliability Group @ PoliTO (PhD Computer and Control Engineering - DAUIN Politecnico di Torino). Safety-critical systems, in domains such as automotive, aerospace, and industrial automation, rely on Software Test Libraries (STLs) to detect hardware faults during operation. STLs are typically assembled from a mix of manual, random, and automated approaches, which often introduces significant redundancy and excess execution time. Our work proposes new preprocessing and acceptance-criteria techniques to make the compaction process more efficient, achieving an average TAT reduction up to 53%. This research is carried out within the RIGOLETTO project, funded by the European Union. 🔬 I also had the privilege of presenting "Processing Functional and Physical Defect Equivalences to Accelerate Cell-Aware Model Generation" on behalf of its authors Reza Khoshzaban, Gianmarco Mongelli, Dorian Ronga, Iacopo Guglielminetti, Michelangelo Grosso, Eric Faehn, Patrick GIRARD, Arnaud Virazel and Riccardo Cantoro, a collaborative work involving Politecnico di Torino, LIRMM and STMicroelectronics. Cell-Aware Test enables significantly more accurate modelling of physical defects inside standard cells compared to classical approaches, but generating these models carries a substantial cost in SPICE simulation time. This paper addresses that bottleneck by identifying transistor defects that are equivalent to known functional faults, and excluding them from the simulation queue. The outcome is a reduction of around 25% in the number of defects requiring full characterisation, with no loss in diagnostic accuracy. Thank you to the VTS community for the thoughtful discussions and warm reception. Looking forward to building on this work. #VTS2026 #VLSI #SemiconductorTesting #EDA #FunctionalSafety #CellAwareTest #PolitecnicodiTorino

Gave a talk this week (April 27, 2026) at the 44th IEEE VLSI Test Symposium at Napa Valley, California next door to the Silicon Valley. Presented the latest developments on the IEEE P3405 standard on Multi Die test architecture & repair methods that I am leading the team with other colleagues in the industry. This standard Is going to define the next generation Chips testing with multiple chiplets integrated together in 3D packages.