JIT: don't kill FP/SIMD/mask regs across x64 write barriers#128778
JIT: don't kill FP/SIMD/mask regs across x64 write barriers#128778EgorBo wants to merge 3 commits into
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The x64 JIT_WriteBarrier / JIT_CheckedWriteBarrier helpers (and all the patched-slot variants: PreGrow/PostGrow/SVR/Region + WriteWatch flavors) never execute any SSE/AVX/AVX-512/EVEX-mask instruction. So XMM/YMM/ZMM and K mask registers can stay live across a write barrier call. Narrow RBM_CALLEE_TRASH_WRITEBARRIER (and the matching GCTRASH mask) from the full RBM_CALLEE_TRASH down to RBM_INT_CALLEE_TRASH_INIT on amd64. Integer callee-trash regs remain conservatively in the kill set to keep _DEBUG runtime builds and DOTNET_UseGCWriteBarrierCopy=0 working. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
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Pull request overview
This PR narrows the amd64 JIT write-barrier register kill masks so FP/SIMD/mask registers can remain live across CORINFO_HELP_ASSIGN_REF and CORINFO_HELP_CHECKED_ASSIGN_REF, matching the documented helper ABI and reducing unnecessary spills.
Changes:
- Documents the amd64 write-barrier helper register preservation/clobbering contract.
- Changes amd64 write-barrier trash and GC-trash masks from full callee-trash to integer-only initial callee-trash registers.
- Keeps conservative integer clobbers for runtime/debug write-barrier variants.
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Will this require write barriers that need to call into C++ code on some paths to spill more around the calls? |
Probably not since we cannot guarantee what is happening in a code compiled by C++. But if that is an issue we need a new JIT-EE API, because we already precisely track registers used by WB on arm64 today (and just removing that will lead to quite big regressions) and we've always been doing that for byref WB that I deleted recently |
| @@ -195,10 +214,12 @@ | |||
| #define RBM_CALLEE_TRASH_NOGC RBM_CALLEE_TRASH | |||
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Are there any other functions that might be worth checking or specializing in emitGetGCRegsKilledByNoGCCall
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I am thinking about CORINFO_HELP_JIT_PINVOKE_BEGIN at very least (might be useful for R2R/NAOT)
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| // Registers no longer containing GC pointers after CORINFO_HELP_ASSIGN_REF and CORINFO_HELP_CHECKED_ASSIGN_REF. | ||
| #define RBM_CALLEE_GCTRASH_WRITEBARRIER RBM_CALLEE_TRASH_NOGC | ||
| #define RBM_CALLEE_GCTRASH_WRITEBARRIER RBM_INT_CALLEE_TRASH_INIT |
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It's not as critical, but I'd presume the same guarantee applies to x86?
What I deliberately did not do
shr rcx, 0Bh), so it must be considered clobbered. Preserving dst would require rewriting all ~20 asm variants._DEBUGruntime variant (JIT_WriteBarrier_Debug) and theDOTNET_UseGCWriteBarrierCopy=0config (RhpAssignRef), both of which touch R10/R11.PS: We probably can do this for APX cc @dotnet/intel
I think it would be nice to preserve
dstregister unchanged (we do that for arm64), but that requires some changes in the ASM helpers.