Intelligent test depends on a strong data chain with full visibility to catch latent defects. In Semiconductor Engineering , Teradyne’s Eli Roth and Damian Megna highlight that real time, data driven control must be balanced with the right sensitivity to protect performance, equipment health, and overall results. Read the full article: https://bit.ly/4dPuuAN
About us
Teradyne brings high-quality innovations such as smart devices, life-saving medical equipment and data storage systems to market, faster. Its advanced test solutions for semiconductors, electronic systems, wireless devices and more ensure that products perform as they were designed. Its robotics offerings include collaborative and mobile robots that help manufacturers of all sizes improve productivity and lower costs.
- Website
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http://www.teradyne.com
External link for Teradyne
- Industry
- Semiconductor Manufacturing
- Company size
- 5,001-10,000 employees
- Headquarters
- North Reading, MA
- Type
- Public Company
- Founded
- 1960
- Specialties
- Electronics Manufacturing, Robotics, Semiconductor Test, Industrial Automation, Production Board Test, System Level Test, Storage Test, Wireless Test, Memory Test, and Silicon Photonics
Locations
Employees at Teradyne
Updates
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HBM is redefining device test requirements as the focus shifts to optimizing data movement, requiring power, signal integrity, and package interactions to be validated together. In Electronic Design, Teradyne’s Ken (Hanh) Lai and Honghui Chen explain how Teradyne is helping customers address the growing complexity of HBM testing as memory architectures advance in AI systems. Read the full article: https://bit.ly/4drV29X
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Teradyne reposted this
Last week, Teradyne held its internal technical conference, Innovate, in sunny southern California. ☀️ This conference is held every other year and brings together engineers from all over the company to present new ideas & talk all things innovation. We kicked off the conference in our Agoura Hills office with demos & tutorials, followed by an opening reception at the Ronald Reagan Library Air Force One Pavilion with an engineer comedian. The next two days were held at the Hyatt Regency Westlake with many technical presentations and keynotes. Here's a conference recap: - 772 total participants - 300+ in person attendees - 13 sites represented - 6 keynote speakers - 53 technical presentations - 33 demos & tutorial sessions - 46 posters - 5 panel sessions & 21 panelists - 15 hackathon teams - 1 mobile app ...and we livestreamed & recorded the whole thing! So employees who could not attend in person could still get in on the action. It was amazing to see the many months of planning come to life. I love planning events like this, it's my favorite part of marketing. #EventMarketing #Events #Conferences #EventPlanning
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🎯 Join Teradyne at the IEEE ETS - European Test Symposium! Hear from Teradyne experts on how device architectures are evolving, the challenges of advanced packaging, and how test must adapt. Get practical insights into testing next-generation devices as complexity, power, and thermal demands increase. Register today: https://bit.ly/4dPZvnl
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Teradyne reposted this
Testing HPC systems for the AI era is one of the most technically demanding challenges the semiconductor industry has ever faced. At the ISIG Executive Summit Taiwan 2026, a panel of five experts tackled it head on. Moderated by Kam Lee, Senior Director of Advanced Packaging Technology and Service at TSMC, the Advanced Testing for HPC Systems panel brought together Raajit Lall, VP Marketing at FormFactor Inc., Jeorge Hurtarte, PhD, MBA, Senior Director and Principal Marketing Strategist in the Compute Test Division at Teradyne, Joe Parks, Chief Technology Officer at Technoprobe, and Dr. Stojan Kanev, General Manager of Advanced Semiconductor Test Division at MPI Corporation. Three defining challenges framed the entire discussion. First, silicon photonics testing. As optical engines get integrated into advanced packaging, testing at wafer and die level is no longer optional. Known-good optical engines are a prerequisite for yield, and the industry is still building the solutions to get there at scale. Second, thermal. HPC products are now exceeding 1000W per reticle and 120W/cm2 power density, well beyond the envelope of existing wafer sort thermal solutions. From Technoprobe's Thermal Dissipation System and 250W/cm2 Ultra-High Performance Thermal Chuck, to Teradyne's Advanced Active Thermal Control methodology and MPI's ±1°C temperature uniformity achieved in co-development with ERS electronic GmbH, the panel laid out what it actually takes to keep HPC silicon cool enough to test reliably. Third, shift-left test coverage. To protect yield in advanced packaging, GPU, XPU, HBM, and interposer silicon must be validated as known-good before integration. That means porting functional test content from final test and system-level test all the way back to wafer and die level, a challenge Teradyne's UltraFLEXplus and Titan HP platforms and Technoprobe's Phantom probe solution are directly addressing as the industry pushes toward 448G. The message from the panel was clear: advanced packaging has fundamentally changed the test problem, and the industry needs to solve it in lockstep with packaging innovation. More from the summit 👉 https://lnkd.in/djYZMw-f #ISIGTaiwan2026 #Semiconductors #AdvancedPackaging #SemiconductorTesting #SiliconPhotonics #HPC #AIHardware #Taiwan Mia Chen, Salah Nasri, Kevin Dei, Jubed Miah, Michelle Yan, Elsa Medin, Sephora Maio, Germantas Kneita
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Congratulations to Marvell Technology’s Andrew Yick for securing the cover story in the latest edition of PIC Magazine & PIC International Conference. We’re excited to see Teradyne Photon 100 featured in the article, which highlights the critical role of scalable optical test in scale-up AI networks. ⬇️ Read the full article using the link in this post
🚀 Cover story from #PhotonicIntegratedCircuitsMagazine - Issue 2! 'Why scale-up AI networks demand scalable optical test' by Andrew Yick, Marvell Technology Scale-up AI networks are pushing optics directly onto switches and AI accelerators. To avoid a manufacturing bottleneck, the industry is shifting optical test from lowparallelism, custom configurations to scalable, automated, IC-style methods. Read below or click the link 🔗 https://lnkd.in/g2Tssre #PICMagazine #PIC #photonicintegratedcircuits
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Stop by Teradyne at Booth #A2 and TestInsight at Booth #C2 at ChipEx to explore smarter semiconductor test from validation to high-volume production. Teradyne’s industry-leading ATE and TestInsight’s design-to-test tools deliver a connected flow from test program bring-up to high volume production. Discover what’s possible with a more connected test strategy.🌟
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Teradyne reposted this
Advanced packaging and testing are only as strong as the people solving their hardest problems. These six experts joining us in Taipei on 12–13 May represent decades of combined experience across wafer probing, substrate innovation, x-ray metrology, IC testing, and semiconductor inspection, and they'll be in one room. Raajit Lall, VP Marketing at FormFactor Inc. — bringing 20+ years of test industry experience spanning RF, wireless, and compliance test instruments for AI technologies including PCI Express, DDR/HBM, and Ethernet. Jeorge Hurtarte, PhD, MBA, Senior Director and Principal Marketing Strategist at Teradyne — co-chair of the IEEE Heterogeneous Integration Roadmap Test Chapter, visiting professor, and one of the compute test industry's most experienced voices. Dr. Stojan Kanev, GM of Advanced Semiconductor Test Division at MPI Corporation — 30+ years of global semiconductor test experience, with over 200 patent applications spanning wafer probing, RF, and silicon photonics measurement. Joe Parks, Chief Technology Officer at Technoprobe — formerly VP at Intel, now focused on probe development for HPC and AI applications, thermal control during test, and testing silicon photonic devices. John Tang, General Manager of FCBGA at AKM Meadville Electronics — on how glass-core ABF substrates are breaking through the limitations of conventional organic packaging, delivering 10x higher interconnect density and a 50% reduction in pattern distortion for next-generation chiplet integration. Ben Peecock, Sr. Director of Business Development at Nordson Test & Inspection — driving advanced x-ray metrology solutions for wafer and panel level applications, helping manufacturers achieve higher yields in the most demanding semiconductor packaging environments. The event is sold out, but the waitlist is open: https://lnkd.in/ewiAQG_H 📅 12–13 May | 📍 Taipei #theISIG #ISIGTaiwan2026 #Semiconductors #AdvancedPackaging #SemiconductorTesting #AIHardware #ExecutiveSummit #Connect #Collaborate #Community Mia Chen, Salah Nasri, Kevin Dei, Jubed Miah, Elsa Medin, Michelle Yan, Sephora Maio, Germantas Kneita
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As AI and data centers push power requirements to their limits, power delivery has become a critical challenge. In our latest blog, Teradyne’s Aik Moh Ng explains how AI’s growth depends on reliable and efficient power delivery and on the ability to validate that power at production scale. 📖 Read the full newsletter to learn more. #AI #DataCenter #SemiconductorTesting #Power
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Last month, our team in Cebu partnered with Semiconductor & Electronics Industries in the Philippines Foundation, Inc. (SEIPI) to deliver a three-day Project Management training for Caraga State University faculty in Butuan City. 🎓 This initiative equipped CSU researchers with practical frameworks and tools to strengthen structured project execution and enhance research outcomes.
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