Game Seven Staffing

Friday words of wisdom.

Run the numbers. Most engineers who've done this say they wished they'd done it sooner. If you're a senior or principal engineer who's never contracted, here's the framework most people skip. Your employer isn't paying your salary. They're paying your salary plus ~30 - 35% on top - payroll taxes, health insurance, 401k match, PTO. A $200k base costs your employer closer to $260k–$270k all-in. That gap is what you absorb when you go contract. So the real question is: does the contract rate cover it? Take your true employer cost. Divide by realistic billable hours - not 2,080, because gaps and ramp time are real. Think 1,700–1,900. That's your break-even hourly. Anything above it is upside. A few honest things worth knowing: The FTE stability argument is weaker than it feels. The 2022–2024 semiconductor correction laid off principal engineers with 20 years in. Contracts end, but engineers who contract plan for it. FTE engineers often don't. At your experience level, contract work doesn't hurt your resume. It reads as in-demand. The exception: if you want to move into management, organizational tenure still matters. It usually makes sense when: your vesting cliff is behind you, you want to compress income, or your current program is winding down. FTE usually wins when: there's real equity upside at an early-stage company, or your financial runway genuinely requires predictability. #SemiconductorEngineering #ContractEngineering #ChipDesign

The semiconductor industry is having a lot of conversations right now about shift-left verification, particularly around earlier bug detection, formal methods at RTL, an architecture-phase sign-off. Here's what isn't getting discussed: Shift-left verification requires engineers who can actually execute formal verification - not just engineers who've heard of JasperGold. Principal-level DV engineers with formal property checking experience and real #tapeout history are one of the thinnest talent pools in the industry right now... thinner than experienced physical design engineers and thinner than DFT architects. The teams that can't find this profile end up in the same place: catching bugs at emulation or post-silicon that formal coverage would have surfaced at RTL freeze. Same bugs, but with a higher cost and a missed window. The discipline is right. The pipeline for the people to execute it isn't keeping up. If you're heading into a tapeout push and your formal verification bench is under-staffed, it's worth a conversation. #semiconductor #designverification #formalverification #SoC #chipdesign #DFT

When your staffing partner just forwards the resumes back to you, you're not hiring... you're doing their job. And theirs. And yours. Again. And again. #semiconductor #engineering #engineerhiring

The distinction Blue Pearl Solutions draws is exactly right; code generation and signoff-quality linting are different problems. LLMs excel at pattern synthesis; Calibre, SpyGlass, and Ascent excel at deterministic rule enforcement. The failure mode isn't using LLMs for RTL, it's conflating generation with verification.

The contract engineers winning this market aren't waiting until month 7 to start the next search. They're running a pipeline; one active, one in late-stage interviews, and one warming up. Full breakdown + placement data in the comments.

We're #hiring a new FPGA Verification Engineer in Costa Mesa, California. Apply today or share this post with your network.

"AI is taking engineering jobs." Except not verification jobs. Not firmware bring-up jobs. Not DFT jobs. The aggregate numbers are hiding a discipline-level story that matters if you're trying to close a tapeout with the right headcount. Read on in the comments.

We're #hiring a new Senior Structural Analysis Engineer, Loads and Dynamics in Costa Mesa, California. Apply today or share this post with your network.

What a beautiful (and sad) story about traces of human creativity and ingenuity left behind in our work and products... and now that may disappear as we rely more and more on AI. Intel's 8086 had the designer's initials in the polysilicon. The craft tradition in chip design is older than most people realize, and it survived the EDA automation wave of the 90s. Will the current AI-assisted layout generation preserve or erase that layer of authorship and creativity?